A typical processing system with video/graphics display capability includes a central processing unit (CPU), a display controller coupled with the CPU by a system bus, a system memory also coupled to the system bus, a frame buffer coupled to the display controller by a local bus, peripheral circuitry (e.g., clock drivers and signal converters), display driver circuitry, and a display unit. The CPU generally provides overall system control and, in response to user commands and program instructions retrieved from the system memory, controls the contents of graphics images to be displayed on the display unit. The display controller, which may for example be a video graphics architecture (VGA) controller, generally interfaces the CPU and the display driver circuitry, exchanges graphics and/or video data with the frame buffer during data processing and display refresh operations, controls frame buffer memory operations, and performs additional processing on the subject graphics or video data, such as color expansion. The display driver circuitry converts digital data received from the display controller into the analog levels required by the display unit to generate graphics/video display images. The display unit may be any type of device which presents images to the user conveying the information represented by the graphics/video data being processed.
The frame buffer, which is typically constructed from dynamic random access memory devices (DRAMs), stores words of graphics or video data defining the color/gray-shade of each pixel of an entire display frame during processing operations such as filtering or drawing images. During display refresh, this "pixel data" is retrieved out of the frame buffer by the display controller pixel by pixel as the corresponding pixels on the display screen are refreshed. Thus, the size of the frame buffer directly corresponds to the number of pixels in each display frame and the number of bits (Bytes) in each word used to define each pixel. The size and performance of frame buffer is dictated by a number of factors such as, the number of monitor pixels, the monitor DOT clock rate, display refresh, data read/write frequency, and memory bandwidth, to name only a few.
It often becomes necessary to operate on selected pixel data within the frame buffer using logic operations in order to effect changes on the display screen. For example, when a cursor crosses a window boundary or when a window is "clicked-on", it may be desirable to change the color of the window for emphasis. Another example is in the implementation of drawing tools which allow the user to control the opacity of a given display window. In presently available systems, a selected byte of data is typically read out of a given location in the frame buffer, modified using a given logic operation and appropriate modifying data, and then written back as modified into the frame buffer. These operations are typically accomplished using either two back-to-back RAS accesses or a read-modify-write cycle. In the first case, two RAS/CAS cycles are required, one to read the unmodified data out of memory and one to write the modified data back into memory. In the second case, one extended RAS/CAS cycle is used during which the data is read out, modified, and written back. In each case, a performance (time) penalty is paid with each byte of data modified. If a large number of bytes are being modified the impact on system performance can be substantial.
Thus, the need has arisen for apparatus, systems and methods for performing logic operations on data stored in a memory. In particular, the need has arisen for apparatus, systems and methods which minimize the performance penalties paid by the presently available systems, especially those systems which require both the performance of multiple read and write cycles, during the process of performing a logic operation on selected bytes of data. Further, such apparatus, systems and methods should be particularly applicable to the performance of logic operations on pixel data being stored in a frame buffer.